You are browsing the IT site. Would you like to be redirected to another country or region to see content and products specific to your location?
US
Video: Mastering DDR5 Signal Integrity and Compliance Testing
Watch our exclusive video with our partner Rohde & Schwarz to learn about the latest testing techniques for DDR5 memory interfaces.
Overview
Operating at multi-gigabit speeds, DDR5 greatly increases the complexity of signal integrity analysis, introducing new challenges for testing and compliance. Engineers must measure tight timing margins between DQ and DQS signals, detect crosstalk and reflections, and apply mask tests to ensure compliance with JEDEC specifications.
In this session, we will focus on signal integrity analysis and compliance testing, demonstrating how to perform advanced analysis using zone triggering, protocol decoding, and automated compliance tests. These tools help engineers and engineering teams to validate layout performance, debug timing issues, and assess system robustness—all key factors in successful DDR5 and next-gen memory designs.
In this video, you will learn about the following topics:
1. Key integration challenges of DDR5 and LPDDR5 SDRAM
2. Advanced tools and techniques for debugging and ensuring signal integrity in DDR memory interfaces
3. Practical methods, including zone triggering, to isolate READ/WRITE sequences
4. Optimising DDR5/LPDDR5 interfaces for maximum performance and reliability
5. Automated compliance testing to guarantee JEDEC standard conformance
Meet the speakers:
Guido Schulze
Product Management
Rohde & Schwarz GmbH & Co. KG
Johannes Ganzert
Senior Application Engineer
Rohde & Schwarz GmbH & Co. KG
Our rental solutions provide the fastest and most cost-effective access to cutting-edge equipment for high-speed digital design and compliance testing. Our extensive inventory includes thousands of ready-to-ship instruments, including options and software for testing PCIe, DDR, Ethernet and MIPI.
