R&D and test engineers who need to characterize serial interfaces of up to 32.0 Gb/s can use the M8061A 2:1 Multiplexer with optional de-emphasis to extend the rate of J-BERT M8020A and J-BERT N4903B pattern generator.
For the most accurate receiver characterization results, the M8061A provides four calibrated de-emphasis taps, which can be extended to eight taps, built-in superposition of level interference and Clock/2 jitter injection. The M8061A is a 2-slot AXIe module that can be controlled via USB from the user interface of J-BERT M8020A as well as N4903B.
| Key Features |
| Expands data rate of J-BERT M8020A up to 32 Gb/s and J-BERT N4903B pattern generator up to 28.4 Gb/s |
| Adjustable positive and negative de-emphasis for up to 8 taps, optional |
| Internal superposition of interference for common-mode and differential mode |
| Transparent to jitter generated by J-BERT M8020A and N4903B |
| Clock/2 jitter can be added |
| Electrical idle |
| Control from J-BERT M8020A and N4903B user interface via USB |
| Benefits |
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| Application Examples for M8061A | Optical transceivers such as 100GBASE-LR4, -SR4 and -ER4, 32G Fibre Channel
SERDES and chip-to-chip interfaces, such as OIF CEI
Backplanes, cables, such as 100GBASE-KR4, -CR4
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| Emulate transmitter De-Emphasis with up to 8 taps | Many multi gigabit serial interfaces use transmitter de-emphasis to compensate for electrical signal degradations caused by printed circuit boards or cables between the transmitter and the receiver ports.
R&D and test engineers who need to characterize receiver ports under realistic and worst case conditions require a pattern generator that allows to accurately emulate transmitter de-emphasis with adjustable multi-tap de-emphasis levels.
The M8061A can be used in combination with J-BERT M8020A
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