The U4164A logic analyzer provides industry’s highest data rate state mode (up to 4 Gb/s), highest deep trace timing mode (up to 10 GHz), and deepest memory (up to 400 Mb), enabling validation and debug of DDR4 or LPDDR4 at data rates over 3.5 Gb/s.
The U4164A logic analyzer module has two modes of operation: quad sample state mode and 10 GHz quarter channel timing mode. Quad sample state mode achieves four different sample positions at two independently adjusted thresholds from a single probe point on each input. Quad sample state mode means less space is required to probe high data rate signals such as DDR4, DDR5, LPDDR4, and LPDDR5 that require different sample positions for read and write data and separate rising edge / falling edge samples for data rates greater than 2.5 Gb/s. Quarter channel (10 GHz) timing mode provides up to 1.6 Gb samples per input. In addition to the new modes of operation, the U4164A logic analyzer module includes multiple new features to help high-speed digital and DDR / LPDDR memory design engineers accelerate turn-on and debugging their systems. The U4164A features a timing mode de-skew control, dual thresholds in dual sample state mode, clock hysteresis control to adjust the state mode sensitivity to noise, and the industry's deepest memory depth option (400 Mb full channel, 800 Mb half-channel, and 1.6 Gb in quarter-channel).
To enhance insight from the U4164A trace captures, the B4661A Memory Analysis sotware offers tools to accelerate setup and configurations for DDR / 2 / 3 / 4 / 5 and LPDDR / 1/ 2 / 3 / 4 / 5 measurements and a variety of licensed options for DDR / 2 / 3 / 4 / 5, LPDDR / 1 / 2 / 3 / 4 / 5 and ONFi (Open NAND Flash interface) memory analysis and acompliance validation.
| Key Features |
| State speed mode options up to 4 Gb/s |
| Quad sample state mode provides four samples at two different thresholds from single probe point |
| Clock hysteresis settings for state mode |
| Full memory depth timing modes up to 10 GHz |
| Up to 400 Mb memory depth options (400 Mb full channel timing, 800 Mb ½ channel timing, 1.6 Gb ¼ channel timing) |
| De-skew interface for timing modes |
| Eye scan technology with up to 5 ps x 5 mV scan increments |
| 12.5 GHz, 256K deep timing zoom |
| Specifications |
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| U4164A Logic Analyzer Module |
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| Model Overview |
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| Model | Description |
| U4164A | Logic analyzer module, 136 ch, 12.5 GHz TZ, 5 GHz timing, 350 MHz base state speed, 2 Mb (memory depth in samples) |
| U4164A-A6J | ANSI Z540-1-1994 calibration |
| State and Timing Speed Options |
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| U4164A-700 | Increase maximum state speed to 700 MHz |
| U4164A-01G | Increase maximum speeds: state to 2.8 Gb/s (1.4 GHz) and timing to 10 GHz |
| U4164A-02G | Increase maximum speeds: state to 4 Gb/s (2.5 GHz) and timing to 10 GHz |
| Memory Depth Options |
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| U4164A-004 | Increase acquisition memory depth to 4 Mb |
| U4164A-008 | Increase acquisition memory depth to 8 Mb |
| U4164A-016 | Increase acquisition memory depth to 16 Mb |
| U4164A-032 | Increase acquisition memory depth to 32 Mb |
| U4164A-064 | Increase acquisition memory depth to 64 Mb |
| U4164A-128 | Increase acquisition memory depth to 128 Mb |
| U4164A-200 | Increase acquisition memory depth to 200 Mb |
| U4164A-400 | Increase acquisition memory depth to 400 Mb |
